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Sheet目录3841

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2009 Microchip Technology Inc.

DS39636D-page 151

PIC18F2X1X/4X1X

15.4.9

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the ECCP module for PWM operation:

Configure the PWM pins, P1A and P1B (and

P1C and P1D, if used), as inputs by setting the

corresponding TRIS bits.

Set the PWM period by loading the PR2 register.

If auto-shutdown is required:

Disable auto-shutdown (ECCP1AS = 0)

Configure source (FLT0, Comparator 1 or

Comparator 2)

Wait for non-shutdown condition

Configure the ECCP module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

Select one of the available output

configurations and direction with the

P1M1:P1M0 bits.

Select the polarities of the PWM output

signals with the CCP1M3:CCP1M0 bits.

Set the PWM duty cycle by loading the CCPR1L

For Half-Bridge Output mode, set the dead-

band delay by loading ECCPDEL<6:0> with the

appropriate value.

If auto-shutdown operation is required, load the

ECCP1AS register:

Select the auto-shutdown sources using the

ECCPAS2:ECCPAS0 bits.

Select the shutdown states of the PWM

output pins using the PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits.

Set the ECCPASE bit (ECCPAS<7>).

Configure the comparators using the CMCON

Configure the comparator inputs as analog

inputs.

If auto-restart operation is required, set the

PRSEN bit (ECCPDEL<7>).

Configure and start TMR2:

Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

10. Enable PWM outputs after a new PWM cycle

has started:

Wait until TMRn overflows (TMRnIF bit is set).

Enable the CCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respective TRIS

bits.

Clear the ECCPASE bit (ECCPAS<7>).

15.4.10

OPERATION IN POWER-MANAGED

MODES

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the ECCP pin is driving a value, it will

continue to drive that value. When the device wakes

up, it will continue from this state. If Two-Speed Start-

ups are enabled, the initial start-up frequency from

INTOSC and the postscaler may not be stable

immediately.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

15.4.10.1

Operation with Fail-Safe

Clock Monitor

If the Fail-Safe Clock Monitor is enabled, a clock failure

will force the device into the power-managed RC_RUN

mode and the OSCFIF bit (PIR2<7>) will be set. The

ECCP will then be clocked from the internal oscillator

clock source, which may have a different clock

frequency than the primary clock.

See the previous section for additional details.

15.4.11

EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

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